US 12,310,082 B1
Transistor with curvilinear gate configuration for improved thermal distribution
Shahed Reza, Albuquerque, NM (US); Maher Salloum, Livermore, CA (US); and Brianna Alexandra Klein, Albuquerque, NM (US)
Assigned to National Technology & Engineering Solutions of Sandia, LLC, Albuquerque, NM (US)
Filed by National Technology & Engineering Solutions of Sandia, LLC, Albuquerque, NM (US)
Filed on Apr. 25, 2022, as Appl. No. 17/728,330.
Claims priority of provisional application 63/257,950, filed on Oct. 20, 2021.
Int. Cl. H10D 64/27 (2025.01); H10D 30/47 (2025.01); H10D 62/824 (2025.01); H10D 62/85 (2025.01)
CPC H10D 64/411 (2025.01) [H10D 30/475 (2025.01); H10D 62/824 (2025.01); H10D 62/8503 (2025.01)] 17 Claims
OG exemplary drawing
 
1. A transistor apparatus of the kind in which a gate electrode includes one or more gate fingers that extend laterally across an active device area between one or more source fingers and one or more drain fingers, wherein:
at least one gate finger describes two or more in-plane meanders about an average path across the active device area;
a shape of the two or more in-plane meanders comprises an amplitude-modulated sinusoid; and
the two or more in-plane meanders are tapered such that a taper amplitude is smallest in a central part of the gate finger and increases toward end portions of the gate finger.