| CPC H10D 64/258 (2025.01) [H10D 30/6219 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 62/118 (2025.01); H10D 84/853 (2025.01); H10D 30/6211 (2025.01); H10D 30/67 (2025.01)] | 20 Claims |
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1. A semiconductor device comprising:
a substrate;
a first active pattern extending in a first horizontal direction on the substrate;
a second active pattern extending in the first horizontal direction on the substrate, the second active pattern being spaced apart from the first active pattern in a second horizontal direction, the second horizontal direction being different from the first horizontal direction;
a field insulating layer surrounding at least a part of side walls of each of the first and second active patterns on the substrate, the field insulating layer including a protrusion protruding upwardly in a vertical direction between the first active pattern and second active pattern;
a first source/drain region on the first active pattern;
a second source/drain region on the second active pattern; and
a source/drain contact electrically connecting the first source/drain region and the second source/drain region with each other, the source/drain contact including a first portion and a second portion, the first portion extending toward the field insulating layer between the first source/drain region and the second source/drain region, the second portion on the first portion,
wherein a lower surface of the first portion of the source/drain contact includes a recess which is recessed upwardly in the vertical direction,
wherein at least a part of the protrusion is inside the recess,
wherein the field insulating layer includes,
a first upper surface between the first active pattern and the protrusion, and
a second upper surface between the second active pattern and the protrusion, and
wherein the second upper surface of the field insulating layer is higher than the first upper surface of the field insulating layer.
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