| CPC H10D 64/112 (2025.01) [H10D 8/60 (2025.01); H10D 30/47 (2025.01)] | 18 Claims |
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1. A field-effect transistor (FET), comprising:
a substrate;
a source electrode and a drain electrode disposed on the substrate;
a channel layer;
a gate electrode structure comprising:
a gate electrode in contact with the channel layer;
a first lateral field plate adjacent to one side of the gate electrode; and
a second lateral field plate adjacent to an opposite side of the gate electrode;
wherein the first and second lateral field plates are disposed in a symmetrical arrangement relative to the gate electrode; and
a first dielectric layer disposed between the first and second lateral field plates and the channel layer; and
wherein the first and second lateral field plates are in contact with the first dielectric layer and are configured to modulate an electric field proximal to the gate electrode proximal to at least one of the drain electrode or the source electrode, or both the drain electrode and the source electrode, and
wherein the gate electrode and the first and second lateral field plates comprise top portions and bottom portions, wherein the bottom portions of the gate electrode and the first and second lateral field plates are buried in an aperture defined in the substrate to a depth extending to the channel layer and the top portions of the gate electrode and the first and second lateral field plates extend above a surface of the substrate.
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