| CPC H10D 64/021 (2025.01) [H10D 30/6757 (2025.01); H10D 62/235 (2025.01); H10D 64/018 (2025.01); H10D 64/518 (2025.01); H01L 21/28141 (2013.01); H10D 30/0293 (2025.01); H10D 30/204 (2025.01); H10D 62/292 (2025.01); H10D 84/0147 (2025.01); H10D 84/038 (2025.01)] | 19 Claims |
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1. A semiconductor device, comprising:
a first active region defined on a substrate and including a plurality of channel regions;
a first gate electrode across the first active region and surrounding a top surface, a side surface, and a bottom surface of at least one of the plurality of channel regions;
a first gate dielectric layer between the first active region and the first gate electrode;
a first drain region in the first active region at a position adjacent to the first gate electrode and in contact with each of the plurality of channel regions;
a first gate spacer on a side surface of the first gate electrode;
a second active region defined in a second region on the substrate;
a second gate electrode across the second active region and having a larger horizontal width than the first gate electrode;
a second drain region in the second active region at a position adjacent to the second gate electrode;
an undercut region between the second active region and a metal portion of the second gate electrode; and
a second gate spacer on a side surface of the second gate electrode and protruding into the undercut region; and
a lower gate dielectric layer between the second active region and the second gate electrode and having a smaller horizontal width than the second gate electrode.
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