US 12,310,071 B2
Semiconductor structure and fabrication method thereof
Chia-Ling Wang, Tainan (TW); Ping-Hung Chiang, Tainan (TW); Wei-Lun Huang, Tainan (TW); Chia-Wen Lu, Tainan (TW); and Ta-Wei Chiu, Changhua County (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Jul. 3, 2024, as Appl. No. 18/762,679.
Application 18/762,679 is a division of application No. 17/577,403, filed on Jan. 18, 2022.
Claims priority of application No. 202111623111.4 (CN), filed on Dec. 28, 2021.
Prior Publication US 2024/0355873 A1, Oct. 24, 2024
Int. Cl. H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 62/115 (2025.01) [H10D 84/0151 (2025.01); H10D 84/038 (2025.01)] 13 Claims
OG exemplary drawing
 
1. A method for fabricating a semiconductor structure, comprising:
providing a substrate comprising a first device region and a second device region in proximity to the first device region;
forming a trench isolation structure in the substrate between the first device region and the second device region;
conformally depositing a mask layer on the substrate to cover the first device region, the second device region, and the trench isolation structure;
forming a first resist pattern on the mask layer, wherein the first resist pattern covers the trench isolation structure and the second device region;
removing the mask layer and a pad oxide layer not covered by the first resist pattern from the first device region, thereby exposing a top surface of the substrate in the first device region;
removing the first resist pattern;
oxidizing the top surface of the substrate in the first device region to form a sacrificial oxide layer;
removing the sacrificial oxide layer to expose the top surface of the substrate in the first device region; and
removing the mask layer to expose a top surface of the trench isolation structure.