| CPC H10D 30/795 (2025.01) [H01L 21/0259 (2013.01); H10D 30/031 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 84/0167 (2025.01); H10D 84/0188 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01)] | 20 Claims |
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1. A method of semiconductor device fabrication, the method comprising:
forming a first fin structure comprising a plurality of semiconductor layers and a second fin structure comprising the plurality of semiconductor layers;
forming a shallow trench isolation (STI) feature interposing a lower portion of the first fin structure and a lower portion of the second fin structure;
providing an opening extending between the first fin structure and the second fin structure, the opening disposed over the STI feature;
forming a first dielectric layer over the STI feature and in a first region of the opening adjacent the first fin structure;
forming a second dielectric layer over the STI feature and in a second region of the opening adjacent the second fin structure, wherein a sidewall of the second dielectric layer extends along a sidewall of the first dielectric layer, wherein the first dielectric layer applies a first stress profile to the first fin structure and the second dielectric layer applies a second stress profile to the second fin structure; and
removing a first set of the plurality of semiconductor layers to form a first plurality of channel regions from the first fin structure and to form a second plurality of channel regions from the second fin structure wherein an upper surface of the first dielectric layer and an uppermost channel region of the first plurality of channel regions are substantially coplanar.
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