US 12,310,064 B2
Isolation pillar structures for stacked device structures
Ruilong Xie, Niskayuna, NY (US); Julien Frougier, Albany, NY (US); Kangguo Cheng, Schenectady, NY (US); Chanro Park, Clifton Park, NY (US); and Min Gyu Sung, Latham, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Jul. 29, 2022, as Appl. No. 17/877,414.
Prior Publication US 2024/0038867 A1, Feb. 1, 2024
Int. Cl. H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H10D 30/6735 (2025.01) [H10D 62/121 (2025.01); H10D 84/0128 (2025.01); H10D 84/038 (2025.01); H10D 84/856 (2025.01)] 25 Claims
OG exemplary drawing
 
1. A microelectronic structure comprising:
a first stacked device structure comprising a first upper device and a first lower device;
a second stacked device structure comprising a second upper device and a second lower device;
an isolation pillar structure located between the first and second stacked device structures;
wherein the isolation pillar structure has an upper section contacting the first and second upper devices and a lower section contacting the first and second lower devices; and
wherein the upper section of the isolation pillar structure has a first width and the lower section of the isolation pillar structure has a second width different than the first width.