| CPC H10D 30/6731 (2025.01) [H10D 30/6729 (2025.01); H10D 30/6745 (2025.01); H10D 30/6757 (2025.01); H10D 62/235 (2025.01)] | 20 Claims |

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1. A semiconductor device, comprising:
an insulating substrate;
a non-planar layer disposed on the insulating substrate and comprising a non-planar structure, wherein the non-planar structure comprises a sidewall; and
an active pattern, wherein at least part of the active pattern is located on the sidewall of the non-planar structure, and the active pattern comprises a channel located on the sidewall;
a gate located on a side of the active pattern away from the sidewall, wherein an orthographic projection of the gate on the insulating substrate overlaps an orthographic projection of the channel on the insulating substrate;
a gate insulating layer disposed between the gate and the active pattern, wherein the gate insulating layer comprises an inclined portion, the inclined portion covers a part of the active pattern on the sidewall, and the gate comprises a gate sidewall located on the inclined portion, wherein the gate sidewall is disposed at a slope angle greater than or equal to 30 degrees and less than or equal to 60 degrees with respect to the inclined portion;
wherein a ratio of a size of the non-planar structure in a thickness direction of the non-planar layer to a thickness of the active pattern is less than or equal to seven.
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