US 12,310,057 B2
Semiconductor devices including backside vias and methods of forming the same
Che-Lun Chang, Hsinchu (TW); Wei-Yang Lee, Taipei (TW); Chia-Pin Lin, Xinpu Township (TW); and Yuan-Ching Peng, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 13, 2024, as Appl. No. 18/741,987.
Application 18/741,987 is a continuation of application No. 17/814,132, filed on Jul. 21, 2022, granted, now 12,040,407.
Application 17/814,132 is a continuation of application No. 17/003,170, filed on Aug. 26, 2020, granted, now 11,417,767, issued on Aug. 16, 2022.
Claims priority of provisional application 63/030,560, filed on May 27, 2020.
Prior Publication US 2024/0339542 A1, Oct. 10, 2024
Int. Cl. H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 30/69 (2025.01); H10D 62/00 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/62 (2025.01)
CPC H10D 30/6713 (2025.01) [H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/28518 (2013.01); H01L 23/5286 (2013.01); H10D 30/031 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 30/797 (2025.01); H10D 62/021 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 64/62 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first semiconductor fin and a second semiconductor fin;
a first stack of nanostructures aligned with the first semiconductor fin;
a second stack of nanostructures aligned with the second semiconductor fin;
a source/drain region adjacent the first stack of nanostructures and the second stack of nanostructures, wherein the source/drain region extends over the first semiconductor fin;
an isolation region between the first semiconductor fin and the second semiconductor fin and along opposing sides of the first semiconductor fin and the second semiconductor fin;
a gate structure extending along sidewalls of the first stack of nanostructures and the second stack of nanostructures;
a first dielectric layer on a surface of the isolation region, the first dielectric layer contacting the first semiconductor fin opposite the first stack of nanostructures, the first dielectric layer contacting the second semiconductor fin opposite the second stack of nanostructures; and
a via extending through the first dielectric layer and the isolation region, the via electrically contacting the source/drain region, wherein a width of the via in the first dielectric layer is greater than a width of the via in the isolation region.