| CPC H10D 30/615 (2025.01) [H10D 62/299 (2025.01); H10D 62/393 (2025.01); H10D 62/8325 (2025.01)] | 15 Claims |
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1. An integrated Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)-Junction Field-Effect Transistor (JFET) device comprising:
a drain contact formed on a backside of a highly-doped semiconductor substrate having a first dopant type with a high concentration;
a substrate formed on a frontside of the highly-doped semiconductor substrate, the substrate having a low concentration of the first dopant type;
buried islands formed within the substrate and above the highly-doped semiconductor substrate, the buried islands having a second dopant type with an opposite polarity as the first dopant type, the buried islands separated from a top surface by the substrate and separated from the backside by the substrate;
a trench formed from the top surface into the substrate, the trench having sidewalls and a bottom that are doped with the second dopant type to form a JFET tap that contacts the substrate;
wherein the trench is formed above one of the buried islands, wherein a JFET is formed by the JFET tap and the substrate;
wherein the buried islands are all within a depletion region created during a saturation mode, and wherein a lower buried island in the buried islands is not within the depletion region during the linear mode;
a polysilicon gate formed between the trench and another trench;
a source formed on the top surface next to the polysilicon gate, the source having a high concentration of the first dopant type;
a body region formed underneath the source next to the polysilicon gate, the body region connecting to the JFET tap;
wherein the body region forms a channel of a MOSFET when biased by the polysilicon gate, the channel for conducting current between the source and the substrate;
wherein the body region has a low concentration of the second dopant type, wherein the low concentration is lower than the high concentration by at least one order of magnitude; and
a gate oxide isolating the polysilicon gate from the source, the body region, and the substrate;
wherein the buried islands further comprise:
an uppermost buried island that is separated from the JFET tap by a first separation distance and having a first width;
a middle buried island that is separated from the uppermost buried island by a second separation distance and having a second width;
a lower buried island that is separated from the middle buried island by a third separation distance and having third width;
wherein the first width is wider than the second width, and the second width is wider than the third width;
wherein the uppermost buried island, the middle buried island, and the lower buried island form a tapered structure;
wherein the separation distance is smaller than the second separation distance, and the second separation distance is smaller than the third separation distance;
wherein vertical spacing between the buried islands increases for deeper buried islands deeper in the substrate;
wherein ON resistance through a drift region in the substrate is reduced during the linear mode by increased vertical separation between buried islands deep in the substrate.
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