US 12,310,033 B2
Crossbar array circuit with parallel grounding lines
Ning Ge, Danville, CA (US)
Assigned to TetraMem Inc., Fremont, CA (US)
Filed by TetraMem Inc., Fremont, CA (US)
Filed on Feb. 17, 2023, as Appl. No. 18/170,837.
Application 18/170,837 is a continuation of application No. 17/357,341, filed on Jun. 24, 2021, granted, now 11,610,942.
Application 17/357,341 is a continuation of application No. 16/693,228, filed on Nov. 23, 2019, granted, now 11,069,742, issued on Jul. 20, 2021.
Prior Publication US 2023/0209841 A1, Jun. 29, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 13/00 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10B 63/30 (2023.02) [G11C 13/0002 (2013.01); G11C 13/003 (2013.01); H10B 63/84 (2023.02); H10N 70/253 (2023.02); H10N 70/821 (2023.02); G11C 2213/74 (2013.01)] 10 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a plurality of transistors comprising a first transistor and a second transistor;
an RRAM device connected in series with the first transistor and the second transistor;
a first bit line connected to the RRAM device; and
a grounding line, wherein the grounding line is connected to a first body terminal of the first transistor, wherein the grounding line is parallel to the first bit line.