US 12,310,032 B2
Stacked backend memory with resistive switching devices
Wilfred Gomes, Portland, OR (US); Abhishek A. Sharma, Hillsboro, OR (US); Van H. Le, Beaverton, OR (US); and Hui Jae Yoo, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 8, 2021, as Appl. No. 17/342,144.
Prior Publication US 2022/0392957 A1, Dec. 8, 2022
Int. Cl. H10B 63/00 (2023.01); H10B 61/00 (2023.01)
CPC H10B 63/30 (2023.02) [H10B 61/22 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device, comprising:
a first layer comprising transistors; and
a second layer comprising a memory cell,
wherein:
the memory cell includes a transistor and a resistive switching device,
the transistor has a first region and a second region,
one of the first region and the second region is a source region of the transistor and another one of the first region and the second region is a drain region of the transistor,
the resistive switching device has a first terminal and a second terminal,
the first terminal is coupled to the first region,
the second terminal is coupled to a select-line for the memory cell, and
the second region is coupled to a bit-line for the memory cell.