US 12,310,030 B2
Semiconductor structure and manufacturing method thereof
Xiaoguang Wang, Hefei (CN); Dinggui Zeng, Hefei (CN); Huihui Li, Hefei (CN); and Kanyu Cao, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN); and BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY, Beijing (CN)
Filed on Jun. 23, 2022, as Appl. No. 17/808,372.
Application 17/808,372 is a continuation of application No. PCT/CN2022/077805, filed on Feb. 25, 2022.
Claims priority of application No. 202111020494.6 (CN), filed on Sep. 1, 2021.
Prior Publication US 2023/0066016 A1, Mar. 2, 2023
Int. Cl. H10B 61/00 (2023.01); H10N 50/01 (2023.01)
CPC H10B 61/22 (2023.02) [H10N 50/01 (2023.02)] 12 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a plurality of memory cells alternately arranged on a substrate, one of the plurality of memory cells comprising an odd number of vertical transistors, a connection pad connected to one end of each of the odd number of vertical transistors, and a magnetic tunnel junction located on the connection pad; wherein
a material of a channel of each of the odd number of vertical transistors comprises a monocrystalline semiconductor.