US 12,310,029 B2
Semiconductor memory device and manufacturing method thereof
Yu-Chien Chiu, Hsinchu (TW); Meng-Han Lin, Hsinchu (TW); Chun-Fu Cheng, Hsinchu County (TW); Han-Jong Chia, Hsinchu (TW); Chung-Wei Wu, Hsin-Chu County (TW); and Zhiqiang Wu, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Jun. 7, 2023, as Appl. No. 18/331,138.
Application 18/331,138 is a division of application No. 17/351,121, filed on Jun. 17, 2021, granted, now 11,716,857.
Prior Publication US 2023/0320102 A1, Oct. 5, 2023
Int. Cl. H10B 51/20 (2023.01); H01L 29/06 (2006.01); H10B 51/10 (2023.01); H10B 51/30 (2023.01)
CPC H10B 51/20 (2023.02) [H01L 29/0649 (2013.01); H10B 51/10 (2023.02); H10B 51/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor memory device, the method comprising:
forming a stack of alternating insulating layers and sacrificial layers over a substrate, the stack comprising a memory cell region and a connection region adjoined to the memory cell region and configured in a staircase structure;
forming a plurality of first trenches in the memory cell region of the stack;
filling a portion of each first trench with a first material;
filling the remaining portion of each first trench with a second material;
forming a second trench through the stack between two of the filled first trenches;
removing the sacrificial layers to form recesses between the insulating layers;
depositing a first conductive material in the recesses via the second trenches;
sequentially forming a ferroelectric layer and a semiconductor layer on the sidewalls and bottom of each second trench; and
filling the second trenches with a third material.