US 12,310,023 B2
3D semiconductor device and array layout with isolated conductive pillars
Hang-Ting Lue, Hsinchu (TW); Wei-Chen Chen, Taoyuan (TW); Teng Hao Yeh, Hsinchu County (TW); and Guan-Ru Lee, Hsinchu (TW)
Assigned to MACRONIX International Co., Ltd., Hsinchu (TW)
Filed by MACRONIX International Co., Ltd., Hsinchu (TW)
Filed on Apr. 27, 2023, as Appl. No. 18/308,594.
Application 18/308,594 is a continuation of application No. 16/784,167, filed on Feb. 6, 2020, granted, now 11,678,486.
Claims priority of provisional application 62/856,158, filed on Jun. 3, 2019.
Prior Publication US 2023/0269944 A1, Aug. 24, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 43/27 (2023.01); H01L 23/528 (2006.01); H10B 43/10 (2023.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/311 (2006.01); H10D 64/01 (2025.01); H10D 64/68 (2025.01)
CPC H10B 43/27 (2023.02) [H01L 23/528 (2013.01); H10B 43/10 (2023.02); H01L 21/02164 (2013.01); H01L 21/0217 (2013.01); H01L 21/02271 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H10D 64/037 (2025.01); H10D 64/685 (2025.01); H10D 64/693 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A 3D semiconductor device, comprising:
a gate stack structure disposed on a substrate, and comprising a plurality of gate layers electrically insulated from each other;
a channel pillar disposed on the substrate, penetrating through the gate stack structure and comprising a curved surface;
a first conductive pillar and a second conductive pillar disposed on the substrate, electrically coupled to the channel pillar and penetrating through the gate stack structure, wherein the first conductive pillar and the second conductive pillar are physically separated from each other and are each connected to the channel pillar;
a charge storage structure disposed between each of the plurality of gate layers and the channel pillar;
an insulating pillar disposed between the first conductive pillar and the second conductive pillar, wherein the first conductive pillar and the second conductive pillar are physically separated from each other and electrically isolated by the insulating pillar; and
an insulating layer disposed within the channel pillar,
wherein a material of the insulating layer is different from a material of the insulating pillar.