| CPC H10B 43/27 (2023.02) [H10B 41/27 (2023.02)] | 20 Claims |
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1. A method, comprising:
forming a multi-layered stack having a plurality of insulating layers and a plurality of spacer layers alternately stacked on top of each other in a vertical direction over a substrate in a chip area having a first memory region and a second memory region;
forming a first mask layer covering the second memory region, while leaving the first memory region partially exposed;
with the first mask layer in place, etching the multi-layered stack to form a plurality of first trenches defining a plurality of first memory stacked structures in the first memory region;
forming a plurality of first gate layers, a first memory layer, and a first channel layer in the plurality of first trenches;
removing the first mask layer;
forming a second mask layer covering the first memory region, while leaving the second memory region partially exposed;
with the second mask layer in place, etching the multi-layered stack to form a plurality of second trenches defining a plurality of second memory stacked structures in the second memory region, wherein the first memory stacked structures are of an AND memory, and the second memory stacked structures are of a NAND memory; and
forming a plurality of second gate layers, a second memory layer, and a second channel layer in the plurality of second trenches.
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