| CPC H10B 41/35 (2023.02) [H10B 41/60 (2023.02); H10D 30/0411 (2025.01); H10D 30/6892 (2025.01)] | 5 Claims |
|
1. A semiconductor memory device, comprising:
a substrate;
a plurality of device lines comprising a select gate (SG) line, a control gate (CG) line, an erase gate (EG) line, and a source line elongated in parallel along a first direction from a top view, wherein the CG line is disposed between the EG line and the SG line, the EG line is merged with the CG line, and the source line underlies the EG line in the substrate, wherein the plurality of device lines defines a plurality of memory cells, wherein each of the plurality of memory cells comprises a floating gate disposed under the CG line;
a plurality of drain doping regions of the plurality of memory cells disposed in the substrate and adjacent to the SG line;
a plurality of bit line contacts disposed on the plurality of drain doping regions of the plurality of memory cells, respectively;
a plurality of source doping regions of the plurality of memory cells electrically coupled to the source line in the substrate and disposed under the EG line, wherein each of the plurality of source doping regions is disposed adjacent to a first sidewall of the floating gate;
a plurality of source line contacts disposed on the plurality of source doping regions of the plurality of memory cells, respectively, wherein the plurality of source line contacts is aligned with the plurality of bit line contacts in a second direction that is orthogonal to the first direction from the top view;
a first dielectric layer disposed between the floating gate and the CG line; and
a second dielectric layer disposed between the floating gate and the EG line, wherein the first dielectric layer is thicker than the second dielectric layer.
|