US 12,310,014 B2
Selection gate separation for 3D NAND
Chang Seok Kang, Santa Clara, CA (US); and Tomohiko Kitajima, San Jose, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Aug. 11, 2021, as Appl. No. 17/399,275.
Claims priority of provisional application 63/066,871, filed on Aug. 18, 2020.
Prior Publication US 2022/0059555 A1, Feb. 24, 2022
Int. Cl. H01L 27/11524 (2017.01); G11C 8/14 (2006.01); G11C 16/04 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01)
CPC H10B 41/35 (2023.02) [G11C 8/14 (2013.01); G11C 16/0483 (2013.01); H10B 41/27 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a memory string in a vertical hole extending through a memory stack on a substrate, the memory string comprising at least one select-gate-for-drain (SGD) transistor and at least one memory transistor, the memory stack consisting essentially of alternating layers of an insulator material and a non-replacement word line, the select-gate-for-drain (SGD) transistor comprising the insulator material and the non-replacement word line, the non-replacement word line consisting of a material selected from the group consisting of tungsten (W), molybdenum (Mo), tantalum (Ta), ruthenium (Ru), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re), titanium (Ti), silicon (Si), silicon germanium (SiGe), and germanium (Ge);
a filled slit adjacent to the memory string and integral with the memory stack, the filled slit filled with the insulator material; and
at least two select-gate-for-drain (SGD) isolation regions in the memory stack adjacent to the memory string and the filled slit, the select-gate-for-drain (SGD) isolation regions comprising one or more of silicon oxide (SiOx) or silicon oxynitride (SiON).