US 12,310,010 B2
Transistors with raised extension regions and semiconductor fins
Haitao Liu, Boise, ID (US); Michael Violette, Boise, ID (US); Mark A. Helm, Santa Cruz, CA (US); Guangyu Huang, El Dorado Hills, CA (US); and Vladimir Mikhalev, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Dec. 3, 2020, as Appl. No. 17/110,439.
Prior Publication US 2022/0181341 A1, Jun. 9, 2022
Int. Cl. H10B 41/27 (2023.01); G11C 16/04 (2006.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01); H10D 30/62 (2025.01); H10D 84/83 (2025.01)
CPC H10B 41/27 (2023.02) [G11C 16/04 (2013.01); H10B 43/27 (2023.02); H10D 30/62 (2025.01); H10D 30/6219 (2025.01); H10D 84/834 (2025.01)] 34 Claims
OG exemplary drawing
 
1. A memory, comprising:
an array of memory cells;
a plurality of access lines, each access line of the plurality of access lines commonly connected to control gates of a respective plurality of memory cells of the array of memory cells; and
driver circuitry comprising a plurality of transistors with each transistor of the plurality of transistors having a first source/drain region connected to a respective access line of the plurality of access lines;
wherein a particular transistor of the plurality of transistors comprises:
a semiconductor overlying a substrate, wherein the semiconductor comprises a plurality of fins in a channel of the particular transistor and overlying the substrate, and wherein the semiconductor has a first conductivity type;
a plurality of plugs of a first dielectric, wherein each plug of the plurality of plugs of the first dielectric is formed between a respective pair of fins of the plurality of fins of the semiconductor;
a second dielectric overlying the semiconductor;
a conductor overlying the second dielectric and extending between each pair of fins of the plurality of fins of the semiconductor;
a first extension region base formed in the semiconductor and extending beyond a first edge of the conductor, wherein the first extension region base has a second conductivity type different than the first conductivity type;
a second extension region base formed in the semiconductor and extending beyond a second edge of the conductor opposite the first edge of the conductor, wherein the second extension region base has the second conductivity type;
a first extension region riser formed overlying the first extension region base and having the second conductivity type;
a second extension region riser formed overlying the second extension region base and having the second conductivity type;
the first source/drain region of the particular transistor formed in the first extension region riser, wherein the first source/drain region of the particular transistor has the second conductivity type and has a conductivity level greater than a conductivity level of the first extension region riser; and
a second source/drain region formed in the second extension region riser and connected to a respective voltage node, wherein the second source/drain region has the second conductivity type and has a conductivity level greater than a conductivity level of the second extension region riser;
wherein each fin of the plurality of fins of the semiconductor is devoid of conductive doping below an upper-most surface of each respective plug of the plurality of plugs of the first dielectric; and
wherein the conductor extends between each pair of fins of the plurality of fins of the semiconductor to a level below a bottom-most surface of the first extension region base and below a bottom-most surface of the second extension region base.