US 12,310,007 B2
Semiconductor structure and fabrication method thereof
Chao Lin, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 15, 2022, as Appl. No. 17/945,113.
Claims priority of application No. 202210680638.9 (CN), filed on Jun. 16, 2022.
Prior Publication US 2023/0013735 A1, Jan. 19, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/50 (2023.02) [H10B 12/053 (2023.02); H10B 12/34 (2023.02); H10B 12/482 (2023.02)] 13 Claims
OG exemplary drawing
 
1. A semiconductor structure having an array region and a peripheral region, the semiconductor structure comprising:
a semiconductor substrate;
a memory array structure positioned above the semiconductor substrate in the array region; wherein the memory array structure comprises memory cells arranged in a multi-layer stack and the memory array structure contacts directly with the semiconductor substrate;
a peripheral circuit structure positioned above the semiconductor substrate in the peripheral region; and
a conductive connection structure positioned in the semiconductor substrate, the conductive connection structure being configured to electrically connect the memory array structure and the peripheral circuit structure;
a first dielectric layer, formed in the peripheral region and the array region, the first dielectric layer covering the peripheral circuit structure;
a first interconnection hole and a second interconnection hole, formed in the first dielectric layer, the first interconnection hole being communicated to the peripheral circuit structure, and the second interconnection hole being communicated to the conductive connection structure;
a connection line structure, formed on the first dielectric layer, the connection line structure being configured to electrically connect the peripheral circuit structure to the conductive connection structure through the first interconnection hole and the second interconnection hole, the connection line structure comprises a connection conductive layer positioned above the first dielectric layer and two conductive plugs located in the first interconnection hole and the second interconnection hole;
a second dielectric layer, formed on an upper surface of the first dielectric layer and an upper surface of the connection line structure;
a third dielectric layer, formed on the memory array structure and the second dielectric layer;
a bit line hole, penetrating through the third dielectric layer, the second dielectric layer and the first dielectric layer, wherein the bit line hole is communicated to the conductive connection structure and a source region or drain region of a transistor of the memory cell in each layer; and
a bit line, formed in the bit line hole.