| CPC H10B 12/34 (2023.02) [H01L 21/762 (2013.01); H01L 21/7624 (2013.01); H01L 21/76264 (2013.01); H01L 21/76283 (2013.01); H10B 12/05 (2023.02); H10B 12/053 (2023.02); H10B 12/315 (2023.02); H10B 12/488 (2023.02); H01L 29/1037 (2013.01); H01L 29/4236 (2013.01)] | 18 Claims |
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1. A semiconductor device comprising:
a substrate including a lower semiconductor film, a buried insulating film, and an upper semiconductor film which are sequentially stacked, the buried insulating film includes either silicon nitride or metal oxide;
an element isolation film defining an active region inside the substrate;
a conductive pattern between the element isolation film and the substrate and being in contact with the lower semiconductor film, the buried insulating film, and the upper semiconductor film;
a first gate trench inside the upper semiconductor film;
a first gate insulating film extending conformally along the first gate trench;
a first gate electrode filling a part of the first gate trench on the first gate insulating film;
a second gate trench inside the element isolation film;
a second gate insulating film extending conformally along the second gate trench; and
a second gate electrode filling a part of the second gate trench on the second gate insulating film,
a bottommost side of the element isolation film being inside the lower semiconductor film, and
a bottommost side of the second gate trench being below an entirety of the upper semiconductor film and at a vertical level lower than a bottommost side of the first gate trench and being at a vertical level higher than the bottommost side of the element isolation film.
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