US 12,310,002 B2
Semiconductor device
Jhen-Yu Tsai, New Taipei (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on May 17, 2024, as Appl. No. 18/666,835.
Application 17/454,249 is a division of application No. 16/592,784, filed on Oct. 4, 2019, granted, now 11,217,589, issued on Jan. 4, 2022.
Application 18/666,835 is a continuation of application No. 17/454,249, filed on Nov. 10, 2021, granted, now 12,029,028.
Prior Publication US 2024/0306369 A1, Sep. 12, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 12/00 (2023.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 21/764 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/17 (2025.01); H10D 99/00 (2025.01)
CPC H10B 12/33 (2023.02) [H01L 21/31111 (2013.01); H01L 21/32133 (2013.01); H01L 21/764 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H10B 12/05 (2023.02); H10B 12/482 (2023.02); H10B 12/488 (2023.02); H10D 30/031 (2025.01); H10D 30/6728 (2025.01); H10D 30/6735 (2025.01); H10D 30/6755 (2025.01); H10D 62/292 (2025.01); H10D 99/00 (2025.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first vertical transistor, comprising:
a first channel region;
a first word line wrapping the first channel region; and
a first word line dielectric layer between the first channel region and the first word line;
a second vertical transistor adjacent to the first vertical transistor, comprising:
a second channel region;
a second word line wrapping the second channel region; and
a second word line dielectric layer between the second channel region and the second word line;
a dielectric layer wrapping upper portions of the first word line and the second word line; and
an air gap inserted between lower portions of the first vertical transistor and the second vertical transistor.