| CPC H10B 12/315 (2023.02) [H10B 12/0335 (2023.02); H10B 12/05 (2023.02); H10D 30/031 (2025.01); H10D 30/6728 (2025.01)] | 20 Claims |

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1. A device structure comprising:
a plurality of transistors laterally spaced apart along a first direction on a first level in a first region;
a first plurality of capacitors on a second level, above the first level, wherein a first electrode of the individual ones of the first plurality of capacitors are coupled with a respective transistor in the plurality of transistors; and
a second plurality of capacitors laterally spaced apart along the first direction on the second level in a second region adjacent to the first region, wherein individual ones of the second plurality of capacitors comprise:
a second electrode, a third electrode, and an insulator layer therebetween, wherein the second electrode of the individual ones of the second plurality of capacitors are coupled with a first interconnect on a third level above the second level, a first conductive plate couples the first interconnect and divides the first interconnect into first and second portions, the first portion above the first conductive plate, the first conductive plate above the second portion, the third electrode of the individual ones of the second plurality of capacitors are coupled with a second interconnect, and a second conductive plate couples the second interconnect and divides the second interconnect into third and fourth portions, the third portion above the second conductive plate, the second conductive plate above the fourth portion.
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