US 12,309,997 B2
Semiconductor structure and method for fabricating same
Guangsu Shao, Hefei (CN); Deyuan Xiao, Hefei (CN); Weiping Bai, Hefei (CN); and Yunsong Qiu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN); and Beijing Superstring Academy of Memory Technology, Beijing (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN); and Beijing Superstring Academy of Memory Technology, Beijing (CN)
Filed on Aug. 1, 2022, as Appl. No. 17/878,061.
Claims priority of application No. 202110937532.8 (CN), filed on Aug. 16, 2021.
Prior Publication US 2023/0049171 A1, Feb. 16, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/05 (2023.02) [H10B 12/315 (2023.02); H10B 12/482 (2023.02)] 12 Claims
OG exemplary drawing
 
1. A method for fabricating a semiconductor structure, comprising:
providing a substrate, the substrate comprising a plurality of semiconductor layers arranged at intervals and an isolation layer positioned between adjacent two of the plurality of semiconductor layers, a given one of the plurality of semiconductor layers and the isolation layer being internally provided with trenches, the plurality of semiconductor layers extending in a first direction, the trenches extending in a second direction and being arranged at intervals in the first direction, the second direction being different from the first direction, and each of the trenches comprising a first region, a second region and a third region sequentially distributed in a direction directing from a bottom of the trench to a top of the trench;
forming a sacrificial layer on an inner wall of the trench in the first region and the second region;
forming an insulating layer filling up the trench on a surface of the sacrificial layer, the insulating layer also exposing at least a portion of a surface of the isolation layer;
removing the sacrificial layer in the second region, and removing the isolation layer of a first thickness to form voids surrounding the given semiconductor layer, the voids exposing a portion of a side wall of the given semiconductor layer;
forming a gate dielectric layer on the exposed side wall of the given semiconductor layer;
forming a first gate electrode layer on a portion of the gate dielectric layer, the first gate electrode layer being also positioned on a top surface of a remaining portion of the isolation layer; and
forming a second gate electrode layer on a remaining portion of the gate dielectric layer, a work function value of the second gate electrode layer being different from a work function value of the first gate electrode layer, and the first gate electrode layer and the second gate electrode layer being stacked in a direction directing from the first region to the third region.