US 12,309,519 B2
Readout circuit for reducing noise in analog-to-digital converters and image sensing device including the same
Han Sol Park, Gyeonggi-do (KR); and Shin Hoo Kim, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Jan. 23, 2024, as Appl. No. 18/419,552.
Claims priority of application No. 10-2023-0111033 (KR), filed on Aug. 24, 2023.
Prior Publication US 2025/0071448 A1, Feb. 27, 2025
Int. Cl. H04N 25/78 (2023.01); H04N 25/772 (2023.01)
CPC H04N 25/78 (2023.01) [H04N 25/772 (2023.01)] 17 Claims
OG exemplary drawing
 
1. A readout circuit comprising:
a ramp signal generator configured to generate a ramp signal having first noise;
a sampling circuit configured to generate a pixel sampling signal having second noise by sampling a pixel signal; and
a conversion circuit configured to compare the ramp signal with the pixel sampling signal and offset the first noise and the second noise based on a result of the comparison,
wherein the sampling circuit includes:
a source follower circuit configured to generate a pixel bias voltage corresponding to the pixel signal based on a bias voltage;
a bias sampling circuit configured to sample the pixel bias voltage and generate a sampling voltage to which the second noise is added; and
a buffer circuit configured to generate the pixel sampling signal based on the sampling voltage,
wherein the bias sampling circuit includes:
a sampling switch connected between an input terminal for receiving the pixel bias voltage and a third node to control a switching operation by a first switching control signal; and
a sampling capacitor connected between the third node and a ground voltage input terminal.