US 12,309,076 B1
Load balancer for parallel link networks using weighted round robin scheduling
Eran Gil Beracha, Tel Aviv (IL); Tal Mund, Herzelia (IL); and Gil Mey-Tal, Hod Hasharon (IL)
Assigned to Mellanox Technologies, Ltd., Yokneam (IL)
Filed by MELLANOX TECHNOLOGIES, LTD., Yokneam (IL)
Filed on Dec. 27, 2023, as Appl. No. 18/397,072.
Int. Cl. H04B 7/02 (2018.01); H04L 47/62 (2022.01); G06F 13/14 (2006.01)
CPC H04L 47/623 (2013.01) [H04L 47/6225 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor, comprising one or more circuits to:
map individual weights of a plurality of parallel links to a plurality of bit strings;
transform the plurality of bit strings into a plurality of sparse bit strings;
cause a vector to be generated representing bits interleaved sequentially from the plurality of sparse bit strings; and
schedule, based at least in part on the vector, assignments for the plurality of parallel links.