US 12,309,067 B2
Hardware queue scheduling for multi-core computing environments
Niall McDonnell, Limerick (IE); Gage Eads, Austin, TX (US); Mrittika Ganguli, Tempe, AZ (US); Chetan Hiremath, Portland, OR (US); John Mangan, Shannon (IE); Stephen Palermo, Chandler, AZ (US); Bruce Richardson, Shannon (IE); Edwin Verplanke, Chandler, AZ (US); Praveen Mosur, Gilbert, AZ (US); Bradley Chaddick, Portland, OR (US); Abhishek Khade, Chandler, AZ (US); Abhirupa Layek, Chandler, AZ (US); Sarita Maini, Tempe, AZ (US); Rahul Shah, Chandler, AZ (US); Shrikant Shah, Chandler, AZ (US); William Burroughs, Macungie, PA (US); and David Sonnier, Austin, TX (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 17/637,416
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed Sep. 11, 2020, PCT No. PCT/US2020/050506
§ 371(c)(1), (2) Date Feb. 22, 2022,
PCT Pub. No. WO2021/050951, PCT Pub. Date Mar. 18, 2021.
Claims priority of provisional application 62/979,963, filed on Feb. 21, 2020.
Claims priority of provisional application 62/899,061, filed on Sep. 11, 2019.
Prior Publication US 2022/0286399 A1, Sep. 8, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 47/125 (2022.01); H04L 47/62 (2022.01); H04L 47/625 (2022.01); H04L 47/6275 (2022.01)
CPC H04L 47/125 (2013.01) [H04L 47/62 (2013.01); H04L 47/624 (2013.01); H04L 47/6255 (2013.01); H04L 47/6275 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus for hardware queue scheduling in a multi-core computing environment, the apparatus comprising:
a first core and a second core of a processor; and
circuitry in a die of the processor, at least one of the first core or the second core included in the die, the at least one of the first core or the second core separate from the circuitry, the circuitry to:
enqueue an identifier to a queue implemented with the circuitry, the identifier associated with a data packet;
assign the identifier in the queue to a first core of the processor; and
after obtaining a notification that an execution of an operation on the data packet with the first core has completed, provide the identifier to the second core to cause the second core to distribute the data packet.