US 12,309,008 B1
Passive equalization circuit
Vinod Kumar, Uttar Pradesh (IN); Hajee Mohammed Shuaeb Fazeel, Bengaluru (IN); and Phalguni Bala, Karnataka (IN)
Assigned to Cadence Design Systems Inc., San Jose, CA (US)
Filed by Cadence Design Systems, Inc., San Jose, CA (US)
Filed on Jun. 14, 2023, as Appl. No. 18/334,580.
Int. Cl. H04L 25/03 (2006.01); H04L 25/02 (2006.01)
CPC H04L 25/03878 (2013.01) [H04L 25/028 (2013.01); H04L 25/0292 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A circuit comprising:
a transmitter;
a receiver; and
a passive equalization circuit located between the transmitter and the receiver, wherein a first inductor is located between the transmitter and a primary node net, and a second inductor is located between the primary node net and a pad, and a third inductor is located between the primary node net and the receiver, wherein a plurality of capacitors are located between the primary node net and a primary electrostatic discharge clamp.