US 12,309,007 B2
Analog equalization with peaking and slope control
Itamar Levin, Holon (IL); Tali Warshavsky Grafi, Ramat Gan (IL); Marco Cusmai, Tel Aviv (IL); Ajay Balankutty, Hillsboro, OR (US); Shiva Kiran, Beaverton, OR (US); and Ariel Cohen, Modiin-Maccabim-Reut (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 18, 2020, as Appl. No. 17/127,853.
Prior Publication US 2021/0152404 A1, May 20, 2021
Int. Cl. H04L 25/03 (2006.01)
CPC H04L 25/03878 (2013.01) 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
at least one medium to communicate a signal; and
an analog equalization circuit to perform equalization on the signal, wherein the analog equalization circuit comprises in a single equalization stage:
a resonant circuit comprising an inductor, a resistance, and a capacitance;
a first source-degeneration network comprising a first tunable capacitance in parallel with a first tunable resistance; and
a second source-degeneration network comprising a second tunable capacitance in parallel with a second tunable resistance.