US 12,309,003 B2
Data receiving circuit, data receiving system, and storage apparatus
Feng Lin, Hefei (CN)
Assigned to Changxin Memory Technologies, Inc., Hefei (CN)
Filed by Changxin Memory Technologies, Inc., Anhui (CN)
Filed on Aug. 10, 2023, as Appl. No. 18/232,489.
Application 18/232,489 is a continuation of application No. PCT/CN2022/128993, filed on Nov. 1, 2022.
Claims priority of application No. 202211124797.7 (CN), filed on Sep. 15, 2022.
Prior Publication US 2024/0097946 A1, Mar. 21, 2024
Int. Cl. H04L 25/03 (2006.01); H04B 1/16 (2006.01)
CPC H04L 25/03057 (2013.01) [H04B 1/16 (2013.01); H04L 2025/03789 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A data receiving circuit, comprising:
a receive circuit, configured to receive a data signal from one of data ports and a reference signal, compare the data signal with the reference signal in response to a sampling clock signal, and output a first output signal and a second output signal; and
a decision feedback equalization circuit, connected to a feedback node of the receive circuit and configured to perform decision feedback equalization on the receive circuit based on a feedback signal to adjust the first output signal and the second output signal, wherein the feedback signal is obtained based on previously received data, the decision feedback equalization circuit responds to a first control signal group and a second control signal group to adjust a capability to adjust the first output signal and the second output signal, the first control signal group corresponds to one of the data ports corresponding to the data signal, and the second control signal group corresponds to all of the data ports, wherein the decision feedback equalization circuit comprises:
a first adjustment circuit, configured to adjust an equivalent resistance value of the first adjustment circuit in response to a first encoded signal group, wherein the equivalent resistance value of the first adjustment circuit is denoted as a first resistance value, and the first encoded signal group is obtained by performing first compilation on the first control signal group and/or the second control signal group; and
a second adjustment circuit, connected in parallel to the first adjustment circuit and configured to adjust an equivalent resistance value of the second adjustment circuit in response to a second encoded signal group, wherein the equivalent resistance value of the second adjustment circuit is denoted as a second resistance value, and the second encoded signal group is obtained by performing second compilation on the first control signal group or the second control signal group,
wherein an equivalent resistance value of the first adjustment circuit and the second adjustment circuit is related to a capability of the decision feedback equalization circuit to adjust the first output signal and the second output signal.