US 12,308,958 B2
Fast converging low-density parity-check techniques
Pinar Sen, San Diego, CA (US); Wei Yang, San Diego, CA (US); Jing Jiang, San Diego, CA (US); Gabi Sarkis, San Diego, CA (US); and Thomas Joseph Richardson, South Orange, NJ (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Aug. 15, 2023, as Appl. No. 18/450,280.
Prior Publication US 2025/0062857 A1, Feb. 20, 2025
Int. Cl. H04L 1/00 (2006.01); H03M 13/00 (2006.01); H03M 13/11 (2006.01)
CPC H04L 1/0041 (2013.01) [H03M 13/1102 (2013.01); H03M 13/116 (2013.01); H03M 13/6362 (2013.01); H03M 13/6368 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A transmitting device, comprising:
one or more memories storing processor-executable code; and
one or more processors coupled with the one or more memories and individually or collectively operable to execute the code to cause the transmitting device to:
perform a lifting procedure on a base graph comprising a plurality of variable nodes and a plurality of check nodes to obtain a lifted graph based at least in part on replacing each edge between the plurality of variable nodes and the plurality of check nodes of the base graph with a respective plurality of identity matrices with respective circular shift values, wherein a punctured variable node of the plurality of variable nodes corresponds to each of one or more check nodes of the plurality of check nodes via a plurality of edges;
encode a plurality of information nodes and a plurality of parity nodes according to the lifted graph; and
transmit a signal comprising a plurality of information bits and a plurality of parity bits based at least in part on encoding the plurality of information nodes and the plurality of parity nodes.