US 12,308,910 B2
Optimizing bias voltages in RIS aided communications
Narayan Prasad, Westfield, NJ (US); Yavuz Yapici, Florham Park, NJ (US); Tao Luo, San Diego, CA (US); and Junyi Li, Fairless Hills, PA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Feb. 7, 2023, as Appl. No. 18/165,918.
Prior Publication US 2024/0267096 A1, Aug. 8, 2024
Int. Cl. H04L 5/12 (2006.01); H04B 7/0456 (2017.01); H04B 7/145 (2006.01); H04W 28/086 (2023.01)
CPC H04B 7/0456 (2013.01) [H04B 7/145 (2013.01); H04W 28/086 (2023.05)] 30 Claims
OG exemplary drawing
 
1. An apparatus for wireless communication at a network node, comprising:
a memory; and
at least one processor coupled to the memory and, based at least in part on information stored in the memory, the at least one processor is configured to:
receive a reconfigurable intelligent surface (RIS) pattern configuration from a network entity;
receive a diode bias voltage configuration for a plurality of diodes or a plurality of RIS elements of the network node from the network entity, the diode bias voltage configuration being associated with the RIS pattern configuration; and
forward at least one transmission from a first device to a second device via the network node in one of an uplink, a downlink, or a sidelink based on the RIS pattern configuration and the diode bias voltage configuration.