US 12,308,854 B2
Digitally enhanced digital-to-analog converter resolution
Mohammad Honarparvar, Gatineau (CA); Sadok Aouini, Gatineau (CA); Jerry Yee-Tung Lam, Stittsville (CA); Soheyl Ziabakhsh Shalmani, Kanata (CA); and Naim Ben-Hamida, Nepean (CA)
Assigned to Ciena Corporation, Hanover, MD (US)
Appl. No. 18/031,188
Filed by Ciena Corporation, Hanover, MD (US)
PCT Filed Oct. 29, 2021, PCT No. PCT/US2021/057349
§ 371(c)(1), (2) Date Apr. 11, 2023,
PCT Pub. No. WO2022/094272, PCT Pub. Date May 5, 2022.
Application 18/031,188 is a continuation of application No. 17/085,520, filed on Oct. 30, 2020, granted, now 11,171,664, issued on Nov. 9, 2021.
Prior Publication US 2023/0412187 A1, Dec. 21, 2023
Int. Cl. H03M 1/66 (2006.01); H03M 1/06 (2006.01); H03M 1/20 (2006.01); H03M 1/68 (2006.01); H03M 1/74 (2006.01)
CPC H03M 1/661 (2013.01) [H03M 1/0607 (2013.01); H03M 1/0682 (2013.01); H03M 1/20 (2013.01); H03M 1/68 (2013.01); H03M 1/742 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A digital-to-analog converter (DAC) comprising:
a decoder circuit configured to convert a N-bit input data to at least N code bits; and
a digital enhancement circuit connected to the decoder circuit, the digital enhancement circuit configured to
logically operate on a least significant bit (LSB) of the N-bit input data;
control a least significant DAC unit of at least N DAC units;
output a factored nominal current or voltage based on the control of the least significant DAC unit and a logical operation, wherein the logical operation outputs a specific logic level based on the LSB; and
output a nominal current or voltage, based on the control of the least significant DAC unit, absent output of the specific logic level from the logical operation, wherein a resolution of the DAC with the at least N DAC units is N+1 bits.