US 12,308,851 B2
Companding analog current to digital converter
Phuong Huynh, Fairfax, VA (US)
Assigned to SIGMASENSE, LLC., Austin, TX (US)
Filed by SIGMASENSE, LLC., Wilmington, DE (US)
Filed on Dec. 5, 2023, as Appl. No. 18/529,134.
Application 18/529,134 is a continuation of application No. 18/092,959, filed on Jan. 4, 2023, granted, now 11,863,197.
Application 18/092,959 is a continuation of application No. 17/503,435, filed on Oct. 18, 2021, granted, now 11,569,828, issued on Jan. 31, 2023.
Application 17/503,435 is a continuation of application No. 17/083,463, filed on Oct. 29, 2020, granted, now 11,152,948, issued on Oct. 19, 2021.
Application 17/083,463 is a continuation of application No. 16/678,793, filed on Nov. 8, 2019, granted, now 10,862,492, issued on Dec. 8, 2020.
Prior Publication US 2024/0113719 A1, Apr. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 1/06 (2006.01); H03M 1/12 (2006.01); H03M 1/46 (2006.01); H03M 1/84 (2006.01); H03M 3/00 (2006.01)
CPC H03M 1/0626 (2013.01) [H03M 1/1245 (2013.01); H03M 1/462 (2013.01); H03M 1/464 (2013.01); H03M 1/84 (2013.01); H03M 3/32 (2013.01); H03M 3/43 (2013.01); H03M 3/462 (2013.01); H03M 3/476 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A companding analog to digital converter (ADC) comprising:
a capacitor that is operably coupled to a load and configured to produce a load voltage based on charging by a load current and a digital to analog converter (DAC) output current, wherein the ADC is coupled to the load via a single line;
a comparator, wherein, when enabled, the comparator operably coupled and configured to generate a comparator output signal based on the load voltage and a reference voltage;
a digital circuit that is operably coupled to the comparator, wherein, when enabled, the digital circuit configured to process the comparator output signal to generate a first digital output signal that is representative of a difference between the load voltage and the reference voltage;
memory that stores operational instructions;
one or more processing modules operably coupled to the digital circuit and the memory, wherein, when enabled, the one or more processing modules is configured to execute the operational instructions to process the first digital output signal to generate a second digital output signal that is representative of the difference between the load voltage and the reference voltage; and
a non-linear N-bit digital to analog converter (DAC) that is operably coupled to the one or more processing modules, wherein, when enabled, the non-linear N-bit DAC configured to generate the DAC output current based on a non-linear function of the second digital output signal, wherein N is a positive integer, the DAC output current tracks the load current, and the load voltage tracks the reference voltage.