US 12,308,850 B2
Low jitter clock multiplier circuit and method with arbitrary frequency acquisition
Hemesh Yasotharan, Toronto (CA); Navid Yaghini, Pickering (CA); Zhuobin Li, Markham (CA); Clifford Ting, Toronto (CA); and Robert Wang, Toronto (CA)
Assigned to Cadence Design Systems, Inc., San Jose, CA (US)
Appl. No. 18/254,522
Filed by Cadence Design Systems, Inc., San Jose, CA (US)
PCT Filed Nov. 25, 2021, PCT No. PCT/US2021/060884
§ 371(c)(1), (2) Date May 25, 2023,
PCT Pub. No. WO2022/115650, PCT Pub. Date Jun. 2, 2022.
Claims priority of provisional application 63/118,714, filed on Nov. 26, 2020.
Prior Publication US 2024/0106444 A1, Mar. 28, 2024
Int. Cl. H03L 7/183 (2006.01); H03L 7/081 (2006.01)
CPC H03L 7/183 (2013.01) [H03L 7/0818 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A clock generation circuit for generating a clock signal at a desired frequency based on a high-frequency clock signal, the high-frequency clock signal having a frequency equal to the desired frequency multiplied by a frequency multiple, comprising:
a clock divider configured to apply a divide ratio to the high-frequency clock signal to generate a divided clock signal, the divide ratio being equal to the frequency multiple rounded up or down to an integer value;
a variable skew control block configured to:
apply a delay to the divided clock signal to generate a first portion of a feedback clock signal such that an edge of the first portion of the feedback clock is delayed to coincide with a corresponding edge of the high-frequency clock signal divided by the frequency multiple; and
repeat one or more times a step of applying an additional delay to the divided clock signal to generate one or more additional portions of the feedback clock signal such that an edge of each additional portion of the feedback clock is delayed to coincide with a corresponding edge of the high-frequency clock signal divided by the frequency multiple.