US 12,308,849 B2
Frequency synthesis using a frequency dividing circuit
Denis Michael Flores Pazos, Grenoble (FR); Andreia Cathelin, Laval (FR); and Yann Deval, Lege Cap-Ferret (FR)
Filed by STMICROELECTRONICS INTERNATIONAL N.V., Geneva (CH); CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, Paris (FR); INSTITUT POLYTECHNIQUE DE BORDEAUX, Talence (FR); and UNIVERSITE DE BORDEAUX, Bordeaux (FR)
Filed on Jun. 30, 2023, as Appl. No. 18/345,298.
Prior Publication US 2025/0007526 A1, Jan. 2, 2025
Int. Cl. H03L 7/18 (2006.01); H03L 7/099 (2006.01)
CPC H03L 7/1806 (2013.01) [H03L 7/0992 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A frequency synthesizer comprising:
a controlled oscillator configured to generate an oscillator output signal and a complement of the oscillator output signal;
a frequency dividing circuit configured to:
receive the controlled oscillator output signal and the complement of the controlled oscillator output signal;
receive a positive binary word and a negative binary word; and
generate a frequency dividing circuit output signal from the controlled oscillator output signal and the complement of the controlled oscillator output signal using the positive binary word and the negative binary word, wherein a ratio of a frequency dividing circuit output signal frequency to a controlled oscillator output signal frequency is a decimal value greater than zero and less than one and is determined using a ratio of a value of the positive binary word to a sum of the value of the positive binary word and an absolute value of the negative binary word.