US 12,308,848 B2
Phase-locked loop device and operation method thereof
Jusung Lee, Suwon-si (KR); Wonsik Yu, Suwon-si (KR); Youngwoo Jo, Suwon-si (KR); and Wooseok Kim, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 3, 2023, as Appl. No. 18/142,939.
Claims priority of application No. 10-2022-0128090 (KR), filed on Oct. 6, 2022.
Prior Publication US 2024/0120927 A1, Apr. 11, 2024
Int. Cl. H03L 7/091 (2006.01); H03L 7/089 (2006.01)
CPC H03L 7/091 (2013.01) [H03L 7/089 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A phase-locked loop device comprising:
a voltage controlled oscillator configured to generate an output clock signal;
a divider configured to divide the output clock signal into a first phase division signal and a second phase division signal, the first phase division signal and the second phase division signal having a constant phase difference;
a sampling phase frequency detector configured to sample, based on the first phase division signal, a sampling voltage generated at a sampling node according to a reference clock signal and output, based on the second phase division signal, any one of the sampling voltage, a first supply voltage, and a second supply voltage having a lower level than the first supply voltage to a hold node;
a transconductance circuit configured to output a conversion current based on a hold voltage generated at the hold node; and
a loop filter configured to generate a voltage control signal based on the conversion current and output the voltage control signal to the voltage controlled oscillator.