US 12,308,845 B2
Reducing duty cycle mismatch of clocks for clock tracking circuits
Waleed El-halwagy, Ottawa (CA); Youcef Fouzar, Ottawa (CA); Kristopher Kshonze, Ottawa (CA); William Roberts, Highland, UT (US); and Faizal Warsalee, Sittsville (CA)
Assigned to Microchip Technology Incorporated, Chandler, AZ (US)
Filed by Microchip Technology Incorporated, Chandler, AZ (US)
Filed on Feb. 10, 2023, as Appl. No. 18/167,722.
Claims priority of provisional application 63/367,434, filed on Jun. 30, 2022.
Prior Publication US 2024/0007111 A1, Jan. 4, 2024
Int. Cl. H03L 7/081 (2006.01); H03K 5/135 (2006.01); H03K 5/156 (2006.01); H03K 7/08 (2006.01)
CPC H03L 7/0812 (2013.01) [H03K 5/135 (2013.01); H03K 5/1565 (2013.01); H03K 7/08 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method, comprising:
comparing a first value and a second value, the first value representing a duty cycle of a reference clock and the second value representing a duty cycle of an output clock generated by a clock tracking circuit to track the reference clock;
setting a duty cycle of a changed clock to reduce duty cycle mismatch between the reference clock and the output clock indicated by the comparing; and
providing the changed clock having set duty cycle in lieu of the one of the reference clock or the output clock.