US 12,308,844 B2
Adaptive cyclic delay line for fractional-N PLL
Noam Familia, Modiin (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 22, 2021, as Appl. No. 17/532,119.
Prior Publication US 2023/0163766 A1, May 25, 2023
Int. Cl. H03L 7/081 (2006.01); H03L 7/093 (2006.01); H03L 7/197 (2006.01)
CPC H03L 7/081 (2013.01) [H03L 7/093 (2013.01); H03L 7/1976 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a phase detector to compare a phase of an input clock to a phase of a feedback clock and output a corresponding phase error signal;
a loop filter coupled to the phase detector;
an oscillator coupled to the loop filter, the loop filter to set a frequency of an output clock at an output terminal of the oscillator based on the phase error signal; and
a feedback path between the output terminal of the oscillator and an input terminal of the phase detector, the feedback path comprising a fractional divider and a delay circuit, the fractional divider to provide a divided version of the output clock, and the delay circuit, to provide the feedback clock, is to apply progressively larger delays to the divided version of the output clock in each division cycle of successive division cycles.