US 12,308,843 B2
Multiple-reference-embedded comparator and comparison method thereof
Jia-Ching Wang, Taipei (TW); and Tai-Haur Kuo, Tainan (TW)
Assigned to National Cheng Kung University, Tainan (TW)
Filed by National Cheng Kung University, Tainan (TW)
Filed on Aug. 16, 2023, as Appl. No. 18/234,874.
Prior Publication US 2025/0062757 A1, Feb. 20, 2025
Int. Cl. H03K 5/24 (2006.01)
CPC H03K 5/2472 (2013.01) 8 Claims
OG exemplary drawing
 
1. A multiple-reference-embedded comparator (MREC) circuit, comprising:
a tail current source circuit;
an input transistor pair, coupled to the tail current source circuit, configured to receive differential input voltages and perform a first pre-amplification to generate first differential amplified voltages according to the differential input voltages; and
a plurality of embedded reference (ER) circuits, each coupled to the input transistor pair, each configured to perform a second pre-amplification to generate second differential amplified voltages according to the first differential amplified voltages, and to perform a discrete-time comparison to generate differential output voltages according to the second differential amplified voltages;
wherein each of the plurality of ER circuits comprises:
an adjustor circuit, coupled to the input transistor pair, configured to perform the second pre-amplification to generate the second differential amplified voltages according to the first differential amplified voltages and differential bias voltages; and
a latch circuit, coupled to the adjustor circuit, configured to perform the discrete-time comparison to generate the differential output voltages according to the second differential amplified voltages.