| CPC H03K 5/01 (2013.01) [G04F 10/005 (2013.01); H03K 3/037 (2013.01)] | 19 Claims |

|
1. A frequency calibration (FCAL) circuit, comprising:
a controllable oscillator, configured to generate a controllable oscillation clock according to a calibration code, wherein an oscillation frequency of the controllable oscillation clock is controlled according to the calibration code;
a divider, coupled to the controllable oscillator, configured to divide the oscillation frequency of the controllable oscillation clock by a predetermined divisor to generate a divided clock;
a time-to-digital converter (TDC), coupled to the divider, configured to convert a first period between a first edge of a reference clock and a first edge of the divided clock into a first period code and convert a second period between a second edge of the reference clock and a second edge of the divided clock into a second period code; and
a calibration logic, coupled to the controllable oscillator and the TDC, configured to compare the first period code and the second period code to generate a comparison result for determining whether the first period is greater or less than the second period, and control the calibration code according to the comparison result.
|