| CPC H03K 3/0231 (2013.01) [H03K 3/014 (2013.01); H03K 3/354 (2013.01)] | 12 Claims |
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1. A relaxation oscillator, comprising:
a voltage-controlled current circuit receiving a first supply voltage, and comprising a first current path, a second current path, a third current path and a fourth current path, wherein the first current path is coupled to a first node, the second current path is coupled to a second node, the third current path is coupled to a third node, the fourth current path is coupled to a fourth node, and a voltage at the second node is a first output signal of the relaxation oscillator;
a first transistor, wherein a first drain/source terminal of the first transistor is connected with the second node, a second drain/source terminal of the first transistor is connected with a fifth node, and a gate terminal of the first transistor is connected with the first node;
a second transistor, wherein a first drain/source terminal of the second transistor is connected with the third node, a second drain/source terminal of the second transistor is connected with the fifth node, and a gate terminal of the second transistor is connected with the fourth node;
a third transistor, wherein a first drain/source terminal of the third transistor is connected with the first node, a second drain/source terminal of the third transistor is connected with the fifth node, and a gate terminal of the third transistor is connected with the third node;
a fourth transistor, wherein a first drain/source terminal of the fourth transistor is connected with the fourth node, a second drain/source terminal of the fourth transistor is connected with the fifth node, and a gate terminal of the fourth transistor is connected with the second node;
a first capacitor connected between the first node and the fifth node;
a second capacitor connected between the fourth node and the fifth node, wherein the fifth node receives a second supply voltage;
a latching circuit wherein a first terminal of the latching circuit is connected with the second node, a second terminal of the latching circuit is connected with the third node, and a third terminal of the latching circuit is connected with the fifth node;
a combinational logic circuit receiving a control signal, and generating a first signal and a second signal;
a fifth transistor, wherein a first drain/source terminal of the fifth transistor is connected with the second node, a second drain/source terminal of the fifth transistor is connected with the fifth node, and a gate terminal of the fifth transistor receives the second signal;
a sixth transistor, wherein a first drain/source terminal of the sixth transistor is connected with the third node, a second drain/source terminal of the sixth transistor is connected with the fifth node, and a gate terminal of the sixth transistor receives the first signal;
a seventh transistor, wherein a first drain/source terminal of the seventh transistor is connected with the first node, a second drain/source terminal of the seventh transistor is connected with the fifth node, and a gate terminal of the seventh transistor receives the second signal; and
an eighth transistor, wherein a first drain/source terminal of the eighth transistor is connected with the fourth node, a second drain/source terminal of the eighth transistor is connected with the fifth node, and a gate terminal of the eighth transistor receives the second signal,
wherein when the control signal is inactivated, the relaxation oscillator is not in a normal working mode, wherein when the control signal is activated, the relaxation oscillator is in the normal working mode.
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