US 12,308,839 B2
RC oscillator
Sheji Li, Beijing (CN); and Sanlin Liu, Beijing (CN)
Assigned to GIGADEVICE SEMICONDUCTOR INC., Beijing (CN)
Filed by GIGADEVICE SEMICONDUCTOR INC., Beijing (CN)
Filed on Sep. 16, 2023, as Appl. No. 18/369,159.
Claims priority of application No. 202211709872.6 (CN), filed on Dec. 29, 2022.
Prior Publication US 2024/0223127 A1, Jul. 4, 2024
Int. Cl. H03K 3/0231 (2006.01); H03K 3/011 (2006.01); H03K 3/354 (2006.01); H03K 4/501 (2006.01)
CPC H03K 3/0231 (2013.01) [H03K 3/011 (2013.01); H03K 3/354 (2013.01); H03K 4/501 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An RC oscillator comprising:
a bias circuit, configured to generate a first bias current and a second bias current, and output a charging current proportional to a total bias current that is the sum of the first bias current and the second bias current, wherein the ratio of the first bias current to the second bias current has a positive temperature coefficient; and
an oscillation circuit, configured to periodically charge a capacitor using the charging current output by the bias circuit, and use a voltage across a resistor through which the second bias current or a current proportional thereto flows as a reference voltage to compare with a charging voltage on the capacitor, so as to obtain a periodically oscillating clock signal;
wherein, the bias circuit comprises:
a first bias current module, comprising a first bias resistor, a first transistor and a second transistor, and configured to generate the first bias current having a positive temperature coefficient or a current proportional to the first bias current on the first bias resistor, wherein a voltage across the first bias resistor is equal to a difference between gate-source voltages of the first transistor and the second transistor, and
a second bias current module, comprising a second bias resistor and a fourth transistor, and configured to generate the second bias current having a negative temperature coefficient or a current proportional to the second bias current on the second bias resistor, wherein a voltage across the second bias resistor is equal to a gate-source voltage of the fourth transistor;
wherein, the first bias current module outputs the first bias current to the second bias current module, and the second bias current module adds the first bias current and the second bias current to generate the total bias current.