US 12,308,838 B1
Exclusive-or logic gate with non-linear input capacitors
Amrita Mathuriya, Portland, OR (US); Rafael Rios, Austin, TX (US); Ikenna Odinaka, Durham, NC (US); Darshak Doshi, Sunnyvale, CA (US); Rajeev Kumar Dokania, Beaverton, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Dec. 11, 2023, as Appl. No. 18/536,091.
Application 18/536,091 is a continuation of application No. 17/659,994, filed on Apr. 20, 2022, granted, now 11,967,954.
Application 17/659,994 is a continuation of application No. 17/659,981, filed on Apr. 20, 2022, granted, now 11,750,197, issued on Sep. 5, 2023.
Int. Cl. H03K 19/23 (2006.01); H03K 19/0185 (2006.01); H03K 19/185 (2006.01)
CPC H03K 19/23 (2013.01) [H03K 19/018521 (2013.01); H03K 19/185 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first capacitor to receive a first input, the first capacitor coupled to a node;
a second capacitor to receive a second input, the second capacitor coupled to the node;
a third capacitor to receive a third input, the third capacitor coupled to the node;
an inverter having an input coupled to the node; and
a NOR gate having an input coupled to an output of the inverter.