US 12,308,837 B1
Multiplier with non-linear polar material
Sasikanth Manipatruni, Portland, OR (US); Yuan-Sheng Fang, Oakland, CA (US); Robert Menezes, Portland, OR (US); Rajeev Kumar Dokania, Beaverton, OR (US); Gaurav Thareja, Santa Clara, CA (US); Amrita Mathuriya, Portland, OR (US); and Ramamoorthy Ramesh, Moraga, CA (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Dec. 11, 2023, as Appl. No. 18/536,061.
Application 18/536,061 is a continuation of application No. 17/503,124, filed on Oct. 15, 2021, granted, now 11,863,183.
Application 17/503,124 is a continuation of application No. 17/129,824, filed on Dec. 21, 2020, granted, now 11,381,244, issued on Jul. 5, 2022.
Int. Cl. H01L 49/02 (2006.01); G06F 7/501 (2006.01); H01L 27/118 (2006.01); H03K 19/23 (2006.01)
CPC H03K 19/23 (2013.01) [G06F 7/501 (2013.01); H01L 27/11807 (2013.01); H01L 2027/11838 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first transistor positioned in a frontend of a die;
a second transistor positioned in the frontend of the die;
a first capacitor positioned above the first transistor and the second transistor;
a second capacitor positioned above the first transistor and the second transistor;
a third capacitor positioned above the first transistor and the second transistor; and
a fourth capacitor having a non-linear polar material, wherein the fourth capacitor is taller than its width, wherein the fourth capacitor is in layers above the first capacitor, the second capacitor, and the third capacitor, and wherein the first transistor and the second transistor are coupled to the fourth capacitor.