US 12,308,835 B2
Level converter
Christian Strittmatter, Rickenbach (DE); Simon Gerwig, Schopfheim (DE); and Harald Schäuble, Lörrach (DE)
Assigned to Endress+Hauser SE+Co. KG, Maulburg (DE)
Appl. No. 18/546,347
Filed by Endress+Hauser SE+Co. KG, Maulburg (DE)
PCT Filed Jan. 27, 2022, PCT No. PCT/EP2022/051858
§ 371(c)(1), (2) Date Aug. 14, 2023,
PCT Pub. No. WO2022/175050, PCT Pub. Date Aug. 25, 2022.
Claims priority of application No. 10 2021 103 807.3 (DE), filed on Feb. 18, 2021.
Prior Publication US 2024/0137021 A1, Apr. 25, 2024
Prior Publication US 2024/0235551 A9, Jul. 11, 2024
Int. Cl. H03K 19/018 (2006.01); H03K 19/0175 (2006.01)
CPC H03K 19/01806 (2013.01) [H03K 19/017518 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A level converter for adjusting a first reference potential and/or a first communication voltage of a first component to a second reference potential and/or a second communication voltage of a second component, wherein the level converter is arranged between the first component and the second component, the level converter comprising:
a first transistor having an input, an output, and a control connection, wherein an open state and a blocked state of the first transistor can be set via the control connection of the first transistor;
a second transistor having an input, an output, and a control connection;
a first resistor connected downstream of the first transistor; and
a second resistor and a third resistor connected in series and forming a voltage divider,
wherein the first reference potential is connected to the output of the second transistor and a second voltage source is connected to the input of the second transistor via the voltage divider of the second and third resistors,
wherein the control input of the first transistor is connected to the input of the second transistor between the second and third resistors,
wherein, in the open state of the first transistor, a current flows through the input and the output of the first transistor,
wherein the output of the first transistor is connected to the second reference potential, and the input of the first transistor is connected to a first voltage source,
wherein the second transistor is configured such that the first transistor is in the open state in an open state of the second transistor and the first transistor is in the blocked state in a blocked state of the second transistor
wherein the level converter is configured such that the second reference potential drops at the first resistor in a blocked state of the first transistor and that the second communication voltage drops at the first resistor in an open state of the first transistor.