US 12,308,829 B2
Bootstrapped switch
Shih-Hsiung Huang, Hsinchu (TW)
Assigned to REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed on Jan. 24, 2024, as Appl. No. 18/420,814.
Application 18/420,814 is a division of application No. 17/828,516, filed on May 31, 2022, granted, now 11,923,831.
Claims priority of application No. 110135350 (TW), filed on Sep. 23, 2021.
Prior Publication US 2024/0171171 A1, May 23, 2024
Int. Cl. H03K 17/06 (2006.01); H03K 17/0412 (2006.01); H03K 19/017 (2006.01)
CPC H03K 17/063 (2013.01) [H03K 17/04123 (2013.01); H03K 19/01735 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A bootstrapped switch that receives an input voltage and outputs an output voltage, comprising:
a first transistor having a first terminal, a second terminal, and a first control terminal, wherein the first transistor receives the input voltage at the first terminal and outputs the output voltage at the second terminal;
a capacitor having a third terminal and a fourth terminal;
a second transistor having a fifth terminal, a sixth terminal, and a second control terminal, wherein the second transistor receives the input voltage at the fifth terminal, the sixth terminal is electrically connected to the third terminal of the capacitor, and the second control terminal is electrically connected to the first control terminal of the first transistor;
a first switch coupled between the third terminal of the capacitor and a first reference voltage;
a second switch coupled between the fourth terminal of the capacitor and a second reference voltage;
a third switch coupled between the fourth terminal of the capacitor and the first control terminal of the first transistor;
a fourth switch coupled to the first transistor and having a third control terminal;
a fifth switch coupled between the fourth switch and the first reference voltage and having a fourth control terminal;
a sixth switch coupled between the third control terminal and a third reference voltage and having a fifth control terminal;
a resistor coupled between the third control terminal and the second reference voltage; and
a logic circuit having a first input terminal and a first output terminal, wherein the first output terminal is coupled to the fifth control terminal;
wherein the fourth control terminal receives a clock, and the first input terminal of the logic circuit receives the clock or an inverted signal of the clock.