| CPC H03F 1/3205 (2013.01) [H03F 3/213 (2013.01)] | 20 Claims |
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1. A structure comprising:
a plurality of auxiliary circuit devices comprising back-gate controls to perform a boost gain; and
a differential pair of circuit devices connected to the plurality of auxiliary circuit devices,
wherein a first transistor of the differential pair of circuit devices shares a gate with a first transistor of the plurality of auxiliary circuit devices and a second transistor of the differential pair of circuit devices shares a separate gate with a second transistor of the plurality of auxiliary circuit devices, and a drain of the first transistor of the differential pair of circuit devices is connected to a drain of the second transistor of the plurality of auxiliary circuit devices, and the differential pair of circuit devices and the plurality of auxiliary circuit devices are formed on a triple-well neighboring n-well layout, and the plurality of auxiliary circuit devices being formed over a shared well.
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