US 12,308,736 B2
Power factor correction circuit
Te-Hung Yu, Taipei (TW); Yu-Cheng Lin, Taipei (TW); Min-Hao Hsu, Taipei (TW); and Chia-Hui Liang, Taipei (TW)
Assigned to LITE-ON TECHNOLOGY CORPORATION, Taipei (TW)
Filed by LITE-ON TECHNOLOGY CORPORATION, Taipei (TW)
Filed on Jun. 13, 2023, as Appl. No. 18/208,953.
Claims priority of application No. 202310264398.9 (CN), filed on Mar. 14, 2023.
Prior Publication US 2024/0313642 A1, Sep. 19, 2024
Int. Cl. H02M 1/42 (2007.01); H02M 1/00 (2006.01); H02M 3/158 (2006.01)
CPC H02M 1/4225 (2013.01) [H02M 1/0064 (2021.05); H02M 3/158 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A power factor correction circuit, comprising:
a first switch including a first terminal and a second terminal;
a second switch including a third terminal and a fourth terminal, wherein the third terminal is connected to the second terminal;
a third switch including a fifth terminal and a sixth terminal, wherein the fifth terminal is connected to the second terminal;
a fourth switch including a seventh terminal and an eighth terminal, wherein the seventh terminal is connected to the first terminal;
a fifth switch including a ninth terminal and a tenth terminal, wherein the ninth terminal is connected to the sixth terminal;
a sixth switch including an eleventh terminal and a twelfth terminal, wherein the eleventh terminal is connected to the first terminal;
a seventh switch including a thirteenth terminal and a fourteenth terminal, wherein the thirteenth terminal is connected to the twelfth terminal, and the fourteenth terminal is connected to the fourth terminal;
a first inductance coil including a fifteenth terminal and a sixteenth terminal, wherein the sixteenth terminal is connected to the second terminal;
a second inductance coil including a seventeenth terminal and an eighteenth terminal, wherein the seventeenth terminal is connected to the tenth terminal, and the eighteenth terminal is connected to the eighth terminal;
a first capacitor including a nineteenth terminal and a twentieth terminal, wherein the nineteenth terminal is connected to the eighth terminal, and the twentieth terminal is connected to the fourth terminal; and
a second capacitor including a twenty-first terminal and a twenty-second terminal, wherein the twenty-first terminal is connected to the first terminal, and the twenty-second terminal is connected to the fourth terminal.