US 12,308,362 B2
Packaging architecture for disaggregated integrated voltage regulators
Kaladhar Radhakrishnan, Chandler, AZ (US); Krishna Bharath, Phoenix, AZ (US); William J. Lambert, Chandler, AZ (US); Adel A. Elsherbini, Tempe, AZ (US); Sriram Srinivasan, Chandler, AZ (US); and Christopher Schaef, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 26, 2021, as Appl. No. 17/412,810.
Prior Publication US 2023/0060727 A1, Mar. 2, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01)
CPC H01L 25/18 (2013.01) [H01L 24/73 (2013.01); H01L 25/0652 (2013.01); H01L 25/50 (2013.01); H01L 23/3128 (2013.01); H01L 23/3185 (2013.01); H01L 23/481 (2013.01); H01L 24/08 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/33 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2924/1427 (2013.01); H01L 2924/19011 (2013.01); H01L 2924/19015 (2013.01); H01L 2924/19042 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A microelectronic assembly, comprising:
a first integrated circuit (IC) die having an electrical load circuit;
a second IC die having a portion of a voltage regulator (VR), wherein:
the second IC die has a first side facing the first IC die and a second side opposite the first side,
the first side comprises first conductive contacts, and
the second side comprises second conductive contacts; and
a third IC die comprising inductors of the VR; wherein:
the third IC die is between the first IC die and the second IC die,
the third IC die has a third side facing the second IC die and a fourth side facing the first IC die,
the third side comprises third conductive contacts coupled with the second conductive contacts,
the fourth side comprises fourth conductive contacts coupled with fifth conductive contacts of the first IC die, and
the VR is configured to receive power at a first voltage and to provide power at a second voltage to the electrical load circuit, the second voltage being lower than the first voltage.